培訓方式以講課和實驗穿插進行
課.程.描.述 ：
第一階段 PrimeTime PX: Signoff Power Analysis
Overview
In this class, you will extend PrimeTime's signoff static timing analysis capability to accurately analyze peak power, average power, clock network power, and multi-voltage power.
A job aid will guide you through the setup requirements and command flow to perform an appropriate power analysis type (average vs. peak; instantaneous peak vs. cycle-accurate peak).
Skills learned include:
- determining possible analysis methods, based on the available data and the application needs
- applying a methodology to confirm that the power analysis performed was complete and correct
- applying debugging technique(s) if necessary
- generating and interpreting all of the standard PrimeTime PX reports for switching activity peak power, average power, clock network power, and multi-voltage power analyses
- generating and viewing peak-power waveforms
To analyze power on multi-voltage designs, you will be using the unified power format (IEEE 1801 UPF) based flow.
- Objectives
- At the end of this workshop the student should be able to:
- Read the required timing and power data; verify their completeness
- Perform peak and average power analysis in the GUI and shell interface
- Perform SDC clock-frequency-based power scaling in VCD/SAIF average power flow
- Generate VCD and SAIF switching activity files by simulating RTL and gate-level designs
- Distinguish between event-based and cycle-accurate peak power (CAPP) analysis
- Dump and view peak power waveforms
- Perform conditional peak power analysis
- Determine quality of analyses from switching activity and power reports
- Estimate pre-layout clock-tree power
- Annotate clock-network power
- Determine power savings due to clock gating
- Specify PVT corner and libraries for multi -voltage power analysis
- Interpret UPF power intent of a multi voltage design
- Perform UPF-flow-based multi-voltage power analysis
- Perform concurrent multi-rail power analysis using UPF
Course Outline
- Introduction to Power Analysis
- Average Power Analysis
- Peak Power Analysis
- Clock Network Power Analysis
- Multivoltage Power Analysi
第二階段 PrimeTime 1
Overview
In this workshop you will learn to perform Static Timing Analysis (STA) using PrimeTime by executing the appropriate high-level summary reports to initiate your analysis, customizing and interpreting detailed timing reports for debugging, and exploring and analyzing the clocks that dictate STA results.
You will also learn to maximize your productivity by validating inherited scripts for your design, by creating scripts using a Synopsys-recommended methodology, by identifying opportunities to improve run time, and by customizing your environment for ease of running and debugging.
The workshop includes comprehensive hands-on labs, which provide an opportunity to apply key concepts covered during the lectures.
- Objectives
- At the end of this workshop the student should be able to:
- Generate summary reports of the design violations organized by clock, by slack, by timing check, or by where they occur: on boundary paths or register-to-register paths.
- Interpret violation details, both for netlist and for constraints, in a timing report for setup and hold, recovery and removal, and clock-gating setup and hold
- Generate timing reports for specific paths and with specific details
- Validate, confirm, debug, enhance, and execute a PrimeTime run script
- Create a PrimeTime run script based on seed scripts from the RMgen (Reference Methodology Generator) utility
- Identify opportunities to improve run time
- Create a saved session and subsequently restore the saved session
- Identify the clocks, where they are defined, and which ones interact, on an unfamiliar design
- Reduce pessimism using path-based analysis
Course Outline
- Unit 1
- Does your Design Meet Timing?
- Objects, Attributes, Collections
- Constraints in a Timing Report
- Timing Arcs in a Timing Report
- Control which Paths are Reported
- Unit 2
- Summary Reports
- Validate & Enhance PrimeTime Session
- Analysis Types and Back Annotation
- Getting to Know Your Clocks
- Unit 3
- Additional Checks and Constraints
- Path-Based Analysis
- Conclusion and Intersecting Technolog
第三階段 PrimeTime 2: Debugging Constraints
Overview
This workshop addresses the most time-consuming part of static timing analysis: debugging constraints. The workshop provides a method to identify potential timing problems, identify the cause, and determine the effects of these problems. Armed with this information, students will now be able to confirm that constraints are correct or, if incorrect, will have sufficient information to correct the problem.
Incorrect STA constraints must be identified because they obscure real timing violations and can cause two problems: either the real violations are missed and not reported or violations are reported that are not real, making it difficult to find the real violations hidden among them.
- Objectives
- At the end of this workshop the student should be able to:
- Pinpoint the cause and determine the effects of check_timing and report_analysis_coverage warnings
- Execute seven PrimeTime commands and two custom procedures to trace from the warning to the cause and explore objects in that path
- Systematically debug scripts to eliminate obvious problems using PrimeTime
- Independently and fully utilize check_timing and report_analysis_coverage to flag remaining constraint problems
- Identify key pieces of a timing report for debugging final constraint problems
Course Outline
- Finding Problems
- Tools of the Trade
- Applying Tools of the Trade to Common Scenarios
- A Recommended Debugging Flow
- Debugging Clocks
- Conclusion
第四階段 PrimeTime SI: Crosstalk Delay and Noise
Overview
In this class, you will learn the basic concepts of crosstalk, their effects on timing and noise, how PrimeTime SI can be used to identify these effects, and how PrimeTime SI can be used to perform hat-if analysis to guide the place and route tools in the fixing of violations. You will apply the PrimeTime SI flow and methodology for chip-level crosstalk analysis. The labs will demonstrate the use of PrimeTime SI to analyze crosstalk failures on an actual design.
Best practice methodologies will give you the insights to drive the PrimeTime SI tool at its optimum performance and to generate quality results.
Hands-on labs follow each training module, allowing you to apply the skills learned in lecture.
- Objectives
- At the end of this workshop the student should be able to:
- Run PTSI for crosstalk delay and noise analysis
- Use the key reports in the shell and GUI to identify violations due to crosstalk, and to guide timing closure
- Define clock relationships for improved timing accuracy
- Apply useful commands to catch and report incomplete inputs to PTSI
- More finely control PTSI and your fixing tool using the following techniques
- Manually control delta delay and noise calculations for specific nets
- Apply path-based analysis
- Apply what-if analysis, both automatically and manually
Course Outline
-
- Run PrimeTime SI: Crosstalk Delay
- Completing your Inputs for PTSI
- Run PrimeTime SI: Crosstalk Noise
- Improving Accuracy
- ECO Flows
第五階段 TetraMAX
Overview
In this three-day workshop, you will learn how use TetraMAX? to perform the following tasks:
- Generate test patterns for stuck-at faults given a scan gate-level design created by DFT Compiler or other tools
- Describe the test protocol and test pattern timing using STIL
- Debug DRC and stuck-at fault coverage problems using the Graphical Schematic Viewer
- Troubleshoot fault coverage problems
- Save and validate test patterns
- Troubleshoot simulation failures
- Diagnose failures on the ATE
This workshop also includes an overview of the fundamentals of manufacturing test, such as:
- What is manufacturing test?
- Why perform manufacturing test?
- What is a stuck-at fault?
- What is a scan chain?
An overview of the Adaptive Scan and Power-Aware APTG features in TetraMAX? will also be presented.
- Objectives
- At the end of this workshop the student should be able to:
- Incorporate TetraMAX? ATPG in a design and test methodology that produces desired fault coverage, ATPG vector count and ATPG run-time for a full-scan or almost full-scan design
- Create a STIL Test Protocol File for a design by using Quick STIL menus or commands, DFT Compiler, or from scratch
- Use the Graphical Schematic Viewer to analyze and debug warning messages from Design Rule Check or fault coverage problems after ATPG
- Describe when and how to use at least three options to increase test coverage and/or decrease the number of required test patterns
- Save test patterns in a proper format for simulation and transfer to an ATE
- Validate test patterns in simulation using MAX Testbench
- Describe the difference between the Transition Delay and Path Delay fault models
- Use timing exceptions with At-Speed testing to mask slow cells
- Limit switching activity with Power-Aware ATPG
- Perform Transition Delay testing including Slack-Based Transition Delay
- Use On-Chip Clocking (OCC) to provide launch and capture clock pulse for At-Speed testing
- Generate critical paths from PrimeTime for performing Path Delay testing
- Use TetraMAX? diagnosis features to analyze failures on the ATE
Course Outline?
Unit 1
- Introduction to ATPG Test
- Building ATPG Models
- Running DRC
- Controlling ATPG
Unit 2
- Minimizing ATPG Patterns
- Pattern Validation
- Introduction to At-Speed Testing
- At-Speed Constraints
Unit 3
- Transition Delay Testing
- On-Chip Clocking Support
- Path Delay Testing
- Diagnosis
- Conclusion
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