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        1、培訓過程中，如有部分內容理解不透或消化不好，可免費在以后培訓班中重聽；
        2、培訓結束后,培訓老師留給學員手機和Email,免費提供半年的技術支持，充分保證培訓后出效果；
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培訓方式以講課和實驗穿插進行。

This course teaches the key features and benefits of the SystemVerilog testbench language and its use in VCS. This course will provide the skills required to write an object-oriented SystemVerilog testbench and verify a device under test with coverage-driven random stimulus.

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Concepts covered during the course include developing an interface between the SystemVerilog test program and the Device Under Test (DUT), random stimulus generation, language syntax, coding style recommendations, object oriented programming concepts, functional coverage and verification methodology (VMM) introduction.

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During lab exercises the student will get practical experience in writing and debugging SystemVerilog testbench code using VCS and testbench debugger (DVE).By the end of this workshop you should be able to:

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●Simulate Verilog designs using VCS
●Debug Verilog designs using VCS
●Run fast RTL-level regression tests for your Verilog design
●Run fast gate-level regression tests for your Verilog design
●Acquire the skills and knowledge to successfully implement coverage driven verification methodology using Synopsys tools

?Unit1

1, VCS Simulation Basics

2, VCS Debugging Basics

3,Debuggin with DVE

4,PostProcessing with VCD + Files

Unit 2

5, Debugging Simulation Mismatches

6, Fast RTL Level Verification

7, Fast Gate level verification

8,Code Coverage