 PrimeRail培訓 |
| 培.養(yǎng).對.象 |
1.理工科背景，有志于數(shù)字集成電路設計工作的學生和轉(zhuǎn)行人員；
2.需要充電，提升技術(shù)水平和熟悉設計流程的在職人員；
3.集成電路設計企業(yè)的員工內(nèi)訓。
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| 入.學.要.求 |
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學員學習本課程應具備下列基礎知識：
◆電路系統(tǒng)的基本概念。 |
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班.級.規(guī).模.及.環(huán).境 |
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為了保證培訓效果，增加互動環(huán)節(jié)，我們堅持小班授課，每期報名人數(shù)限5人，多余人員安排到下一期進行。 |
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上課時間和地點 |
上課地點：【上�！浚和瑵髮W(滬西)/新城金郡商務樓(11號線白銀路站) 【深圳分部】：深圳大學成教院/ 電影大廈(地鐵一號線大劇院站)【北京分部】：福鑫大樓/北京中山學院 【武漢分部】：佳源大廈（高新二路） 【南京分部】：金港大廈(和燕路)
【成都分部】：領館區(qū)1號（中和大道）
最近開課時間(連續(xù)班/周末班/晚班）： PrimeRail培訓開班時間：2025年12月15日..以質(zhì)量贏得尊重節(jié)假日班火熱報名中.....實戰(zhàn)培訓......直播、現(xiàn)場培訓皆可....用心服務..............--即將開課----即將開課，請咨詢客服。 |
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學時 |
◆課時： 共6天,36學時
◆外地學員：代理安排食宿（需提前預定）
☆合格學員免費頒發(fā)相關資格證書，提升您的職業(yè)資質(zhì)
作為最早專注于嵌入式培訓的專業(yè)機構(gòu)，曙海嵌入式學院提供的證書得到本行業(yè)的廣泛認
可，學員的能力得到大家的認同。
☆合格學員免費推薦工作
★實驗設備請點擊這兒查看★ |
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.最.新.優(yōu).惠. |
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◆團體報名優(yōu)惠措施：兩人95折優(yōu)惠，三人或三人以上9折優(yōu)惠 。注意：在讀學生憑學生證，即使一個人也優(yōu)惠500元。 |
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.質(zhì).量.保.障. |
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1、培訓過程中，如有部分內(nèi)容理解不透或消化不好，可免費在以后培訓班中重聽；
2、培訓結(jié)束后,培訓老師留給學員手機和Email,免費提供半年的技術(shù)支持，充分保證培訓后出效果；
3、培訓合格學員可享受免費推薦就業(yè)機會。 ☆合格學員免費頒發(fā)相關工程師等資格證書，提升您的職業(yè)資質(zhì)。專注高端培訓13年，曙海提供的證書得到本行業(yè)的廣泛認可，學員的能力得到大家的認同，受到用人單位的廣泛贊譽。 |
PrimeRail培訓 |
第一階段 |
ObjectivesAt the end of this workshop the student should be able to:
- Set up and perform Power/Ground (PG) reliability analysis for checking Static and Dynamic Voltage Drop and Electromigration (EM) potential violations
- Explanation of and/or set up the phases of Dynamic analysis of PrimeRail that involve the following:
- Library Characterization
- Data preparation
- Power Analysis
- PG Parasitic (RC) Extraction
- Dynamic (Transient) Rail Analysis
- Violation Viewing, Reporting and Correction
- What-if Analysis ? Package parasitics and Decap insertion
- Voltage Drop Derated Timing Analysis
- Accurate Hard Macro Modeling
- Power Management( power switch) Cell handling
- Set up PG analysis for hierarchical and top-level
- Use the PrimeRail graphical user interface (GUI) for the PG rail analysis, including what-if analysis
Audience Profile
Design, verification or CAD engineers who perform power/ground interconnect reliability analysis at the "Block" or "Full-Chip" levels. This covers a wide spectrum of designs of digital, memory, and analog/mixed signal.Prerequisites
Experience in the following areas is recommended to gain the most value from the workshop content:
- Physical layout
- Physical extraction
- Power simulation
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Static Analysis
- Introduction to Rail Analysis - requirements, capabilities and database preparation
- Power and Timing Model creation
- Power supply, net switching and Transition Time inputs
- Power and Rail Analysis
- Mapping, reporting, querying and what-if Analysis
- Integrated Flows - Hardmacro modeling, Power gating and Voltage derated timing analysis
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第二階段 |
Dynamic ( Transient) Analysis
- Introduction, database requirements and flows
- Library Characterization and LSF
- Cell-Level Dynamic Analysis-PP Run
- Cell-Level Dynamic Analysis-Transient Analysis
- What-if Analysis ? Package Parasitics and Decap Insertion
- Mapping, waveform viewing, reporting and querying
- Tx-Level Dynamic Analysis-Data Preparation
- Tx-Level Dynamic Analysis
- Tx-Level Signal EM Analysis
- Macro Modeling - Memory, Analog, custom or Hardmacro blocks
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